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Logic gates
Combination gates
CMOS Quad AND/OR Select Gate
Data sheet
- document-pdfAcrobat CD4019B TYPES datasheet (Rev. C)
CD4019B
Product details
- Medium speed operation……tPHL = tPLH = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) =
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V - Applications:
- AND-OR select gating
- Shift-right/shift-left registers
- True/complement selection
- AND/OR/Exclusive-OR selection
- Medium speed operation……tPHL = tPLH = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) =
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V - Applications:
- AND-OR select gating
- Shift-right/shift-left registers
- True/complement selection
- AND/OR/Exclusive-OR selection
CD4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single-input OR gate. Selection is accomplished by control bits Ka and Kb. In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function.
The CD4019B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single-input OR gate. Selection is accomplished by control bits Ka and Kb. In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function.
The CD4019B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
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Technical documentation
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View all 7| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | CD4019B TYPES datasheet (Rev. C) | 15 Oct 2003 | |
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| User guide | Signal Switch Data Book (Rev. A) | 14 Nov 2003 | ||
| Application note | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | 03 Dec 2001 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
Evaluation board
14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages
The 14-24-LOGIC-EVM evaluation module(EVM)is designed to support any logic device that is in a 14-pin to 24-pinD, DW, DB, NS, PW, DYYor DGV package,
User guide: PDF | HTML
Not available on TI.com
| Package | Pins | Download |
|---|---|---|
| PDIP (N) | 16 | View options |
| SOIC (D) | 16 | View options |
| SOP (NS) | 16 | View options |
| TSSOP (PW) | 16 | View options |
TI's Standard Terms and Conditions for Evaluation Items apply.
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